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  74abt273a octal d-type flip-flop product specification 1995 sep 06 integrated circuits ic23 data handbook
philips semiconductors product specification 74abt273a octal d-type flip-flop 2 1995 sep 06 853-1774 15704 features ? eight edge-triggered d-type flip-flops ? buffered common clock ? buffered asynchronous master reset ? power-up reset ? see 74abt377 for clock enable version ? see 74abt373 for transparent latch version ? see 74abt374 for 3-state version ? esd protection exceeds 2000 v per mil std 833 method 3015 and 200 v per machine model. description the 74abt273a has eight edge-triggered d-type flip-flops with individual d inputs and q outputs. the common buffered clock (cp) and master reset (mr ) inputs load and reset (clear) all flip-flops simultaneously. the register is fully edge-triggered. the state of each d input, one setup time before the low-to-high clock transition, is transferred to the corresponding flip-flop's q output. all outputs will be forced low independent of clock or data inputs by a low voltage level on the mr input. the device is useful for applications where the true output only is required and the cp and mr are common elements. quick reference data symbol parameter conditions t amb = 25 c; gnd = 0v typical unit t plh t phl propagation delay cp to qn c l = 50pf; v cc = 5v 3.0 3.4 ns c in input capacitance v i = 0v or v cc 3.5 pf i cch total supply current outputs high; v cc =5.5v 150 m a ordering information packages temperature range outside north america north america dwg number 20-pin plastic dip 40 c to +85 c 74abt273a n 74abt273a n sot146-1 20-pin plastic so 40 c to +85 c 74abt273a d 74abt273a d sot163-1 20-pin plastic ssop type ii 40 c to +85 c 74abt273a db 74abt273a db sot339-1 20-pin plastic tssop type i 40 c to +85 c 74abt273a pw 7abt273apw dh sot360-1 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 mr q0 d0 d1 q1 q2 d2 d3 q3 q4 gnd d4 d5 q5 q6 d6 d7 q7 v cc cp sa00052 pin description pin number symbol name and function 11 cp clock pulse input (active rising edge) 3, 4, 7, 8, 13, 14, 17, 18 d0 - d7 data inputs 2, 5, 6, 9, 12, 15, 16, 19 q0 - q7 data outputs 1 mr master reset input (active-low) 10 gnd ground (0v) 20 v cc positive supply voltage
philips semiconductors product specification 74abt273a octal d-type flip-flop 1995 sep 06 3 logic symbol (ieee/iec) 11 32 4 5 7 6 89 c1 13 12 14 15 17 16 18 19 1 r 1d sa00054 logic symbol 3 4 7 8 13 14 18 17 d0 d1 d2 d3 d4 d5 d6 d7 q0 q1 q2 q3 q4 q5 q6 q7 2 5 6 9 12 15 16 19 1 11 mr cp sa00053 logic diagram cp q r d d 3 d0 q0 cp q r d d 4 d1 cp q r d d 7 d2 cp q r d d 8 d3 cp q r d d 13 d4 cp q r d d 14 d5 cp q r d d 17 d6 cp q r d d 18 d7 2 q1 5 q2 6 q3 9 q4 12 q5 15 q6 16 q7 19 11 1 cp mr sa00055 function table inputs outputs operating mode mr cp dn q0 - q7 operating mode l x x l reset (clear) h h h load o1o h l l load o0o h = high voltage level h = high voltage level one set-up time prior to the low-to-high clock transition l = low voltage level l = low voltage level one set-up time prior to the low-to-high clock transition x = don't care = low-to-high clock transition
philips semiconductors product specification 74abt273a octal d-type flip-flop 1995 sep 06 4 absolute maximum ratings 1, 2 symbol parameter conditions rating unit v cc dc supply voltage -0.5 to +7.0 v i ik dc input diode current v i < 0 -18 ma v i dc input voltage 3 -1.2 to +7.0 v i ok dc output diode current v o < 0 -50 ma v out dc output voltage 3 output in off or high state -0.5 to +5.5 v i out dc output current output in low state 128 ma t stg storage temperature range -65 to 150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. recommended operating conditions symbol parameter limits unit symbol parameter min max unit v cc dc supply voltage 4.5 5.5 v v i input voltage 0 v cc v v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i oh high-level output current -32 ma i ol low-level output current 64 ma d t/ d v input transition rise or fall rate 0 10 ns/v t amb operating free-air temperature range -40 +85 c
philips semiconductors product specification 74abt273a octal d-type flip-flop 1995 sep 06 5 dc electrical characteristics limits symbol parameter test conditions t amb = +25 c t amb = -40 c to +85 c unit min typ max min max v ik input clamp voltage v cc = 4.5v; i ik = -18ma -0.9 -1.2 -1.2 v v cc = 4.5v; i oh = -3ma; v i = v il or v ih 2.5 2.9 2.5 v oh high-level output voltage v cc = 5.0v; i oh = -3ma; v i = v il or v ih 3.0 3.4 3.0 v v cc = 4.5v; i oh = -32ma; v i = v il or v ih 2.0 2.4 2.0 v ol low-level output voltage v cc = 4.5v; i ol = 64ma; v i = v il or v ih 0.42 0.55 0.55 v v rst power-up output low voltage 3 v cc = 5.5v; i o = 1ma; v i = gnd or v cc 0.13 0.55 0.55 v i i input leakage current v cc = 5.5v; v i = gnd or 5.5v 0.01 1.0 1.0 m a i off power-off leakage current v cc = 0.0v; v o or v i 4.5v 5.0 100 100 m a i cex output high leakage current v cc = 5.5v; v o = 5.5v; v i = gnd or v cc 5.0 50 50 m a i o output current 1 v cc = 5.5v; v o = 2.5v -50 -70 -180 -50 -180 ma i cch quiescent su pp ly current v cc = 5.5v; outputs high, v i = gnd or v cc 150 250 250 m a i ccl q u iescent s u ppl y c u rrent v cc = 5.5v; outputs low, v i = gnd or v cc 24 30 30 ma d i cc additional supply current per input pin 2 v cc = 5.5v; one data input at 3.4v, other inputs at v cc or gnd 0.5 1.5 1.5 ma notes: 1. not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. this is the increase in supply current for each input at 3.4v. 3. for valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. ac characteristics gnd = 0v; t r = t f = 2.5ns; c l = 50pf, r l = 500 w limits symbol parameter waveform t amb = +25 c v cc = +5.0v t amb = -40 c to +85 c v cc = +5.0v 0.5v unit min typ max min max f max maximum clock frequency 1 250 350 250 mhz t plh t phl propagation delay cp to qn 1 1.5 2.0 3.0 3.4 4.0 4.6 1.5 2.0 4.8 4.8 ns t phl propagation delay mr to qn 2 2.5 4.5 6.0 2.5 6.6 ns
philips semiconductors product specification 74abt273a octal d-type flip-flop 1995 sep 06 6 ac setup requirements gnd = 0v; t r = t f = 2.5ns; c l = 50pf, r l = 500 w limits symbol parameter waveform t amb = +25 c v cc = +5.0v t amb = -40 c to +85 c v cc = +5.0v 0.5v unit min typ min t s (h) t s (l) setup time, high or low dn to cp 3 1.5 1.5 0.6 0.4 1.5 1.5 t h (h) t h (l) hold time, high or low dn to cp 3 0.7 0.7 -0.5 -0.5 0.7 0.7 ns t w (h) t w (l) clock pulse width high or low 1 1.5 2.0 0.8 1.0 1.5 2.0 ns t w (l) master reset pulse width, low 2 1.5 0.8 1.5 ns t rec recovery time mr to cp 2 1.5 0.5 1.5 ns ac waveforms v m = 1.5v, v in = gnd to 3.0v the shaded areas indicate when the input is permitted to change for predictable output performance. vm vm vm vm vm 1/f max t w (h) t w (l) t phl t plh cp qn sa00056 waveform 1. propagation delay, clock input to output, clock pulse width, and maximum clock frequency v m sf00158 mr qn v m t w (l) t phl v m t rec cp v m waveform 2. master reset pulse width, master reset to output delay and master reset to clock recovery time t h (h) t s (h) cp sf00191 v m v m v m v m v m v m t h (l) t s (l) dn waveform 3. data setup and hold times
philips semiconductors product specification 74abt273a octal d-type flip-flop 1995 sep 06 7 test circuit and waveforms pulse generator r t v in d.u.t. v out c l r l v cc r l 7.0v test circuit for 3-state outputs v m v m t w amp (v) negative pulse 10% 10% 90% 90% 0v v m v m t w amp (v) positive pulse 90% 90% 10% 10% 0v t thl (t f ) t tlh (t r )t thl (t f ) t tlh (t r ) v m = 1.5v input pulse definition definitions r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators. input pulse requirements family 74abt sa00057 switch position test switch all open amplitude rep. rate t w t f 3.0v 1mhz 500ns 2.5ns t r 2.5ns
philips semiconductors product specification 74abt273a octal d-type flip-flop 8 1995 sep 06 dip20: plastic dual in-line package; 20 leads (300 mil) sot146-1
philips semiconductors product specification 74abt273a octal d-type flip-flop 1995 sep 06 9 so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1
philips semiconductors product specification 74abt273a octal d-type flip-flop 1995 sep 06 10 ssop20: plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1
philips semiconductors product specification 74abt273a octal d-type flip-flop 1995 sep 06 11 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1
philips semiconductors product specification 74abt273a octal d-type flip-flop philips semiconductors and philips electronics north america corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performanc e. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under a ny patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copy right, or mask work right infringement, unless otherwise specified. applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. life support applications philips semiconductors and philips electronics north america corporation products are not designed for use in life support appl iances, devices, or systems where malfunction of a philips semiconductors and philips electronics north america corporation product can reasonab ly be expected to result in a personal injury. philips semiconductors and philips electronics north america corporation customers using or sel ling philips semiconductors and philips electronics north america corporation products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors and philips electronics north america corporation for any damages resulting from such improper use or sale. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 definitions data sheet identification product status definition objective specification preliminary specification product specification formative or in design preproduction product full production this data sheet contains the design target or goal specifications for product development. specifications may change in any manner without notice. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. philips semiconductors and philips electronics north america corporation register eligible circuits under the semiconductor chip protection act. ? copyright philips electronics north america corporation 1995 all rights reserved. printed in u.s.a.


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